As integrated circuits have become increasingly smaller, electrically conductive structures within the integrated circuits are placed increasingly closer together. This situation tends to enhance the inherent problem of parasitic capacitance between adjacent electrically conductive structures. Thus, new electrically insulating materials have been devised for use between electrically conductive structures, to reduce such capacitance problems. The new electrically insulating materials typically have lower dielectric constants, and thus are generally referred to as low k materials. While low k materials help to resolve the capacitance problems described above, they unfortunately tend to introduce new challenges.
Low k materials are typically filled with small voids that help reduce the material's effective dielectric constant. Thus, there is less of the material itself within a given volume, which tends to reduce the structural strength of the material. The resulting porous and brittle nature of such low k materials presents new challenges in both the fabrication and packaging processes. Unless special precautions are taken, the robustness and reliability of an integrated circuit that is fabricated with low k materials may be reduced from that of an integrated circuit that is fabricated with traditional materials, because low k materials differ from traditional materials in properties such as thermal coefficient of expansion, moisture absorption, adhesion to adjacent layers, mechanical strength, and thermal conductivity.
For example, when forming back end of line dual damascene copper interconnect structures, dielectric barrier films, and often a middle etch stop film, is formed between the low k inter layer dielectric layers. The dielectric barrier films perform valuable functions, including forming a diffusion barrier to prevent copper diffusion into the low k inter layer dielectrics, acting as an etch stop layer on top of the copper during the dual damascene via etch process, and acting as a passivation layer to prevent damage, such as exposure to an oxidizing environment and moisture, to the copper during subsequent processing. The middle etch stop layer acts as an etch stop during dual damascene trench etch and enhances the control of the trench depth and the via profile. High etch selectivity between the inter layer dielectric and the middle etch stop layer is generally desired.
It is desirable to have dielectric barrier films and the etch stop films that also have a low dielectric constant, so as to achieve a low overall effective k of the overall dielectric film stack. However, the properties of tradition low k dielectric films have made them inadequate to fulfill the purposes of the barrier and etch stop films. Dielectric barrier and etch stop materials typically include silicon nitride with a k of about seven, silicon carbide with a k of about five, and silicon carbon nitride with a k of about five, deposited using plasma enhanced chemical vapor deposition. These materials have properties that enable them to function well as barriers and etch stops, but they all have relatively high k values.
With the drive toward smaller integrated circuit feature sizes, as mentioned above, and with the use of inter layer dielectrics with lower k values, the dielectric barrier and middle etch stop films tend to have a more significant contribution to the overall effective k value of the dielectric stack in which they are used. When integrated circuit feature sizes become smaller, inter layer dielectric thicknesses tend to become thinner. But the barrier layer and etch stop layer thicknesses do not scale down as much as inter layer dielectric thickness does, due to the requirements on the barrier layers. For example, as the inter layer dielectric thickness decreases from about 7,700 angstroms to about 6,000 to 6,500 angstroms, the dielectric barrier deposition thickness remains substantially constant at about five hundred angstroms. Thus, to reduce the overall dielectric constant of the barrier and middle etch stop films, films with lower k values need to be found.
Plasma enhanced chemical vapor deposition silicon carbide films are very good dielectric barrier and middle etch stop due to their excellent properties, such as good diffusion barrier for copper and moisture, high etch selectivity to carbon doped oxide inter layer dielectric, and industry-friendly plasma enhanced chemical vapor deposition methods. These films are usually deposited at elevated temperatures of between about three hundred centigrade and about four hundred centigrade using trimethylsilane-based chemistry.
One approach to achieve lower k plasma enhanced chemical vapor deposition silicon carbide is to introduce oxygen into the film as it is formed, to reduce the density of the film. This can be accomplished by using precursor gases that include some form of oxygen, such as those with oxygen in their molecular structure, or the introduction of oxygen gas or oxygen-containing gases during the deposition process. Incorporation of oxygen tends to reduce the k value. However, there are problems with oxygenated silicon carbide films. Other approaches to achieving lower k silicon carbide films include the use of novel precursors or post-deposition treatment to increase the porosity of the deposited film. However, these processes are in an early development stage, and as of yet there has been no report of a plasma enhanced chemical vapor deposition oxygen-free silicon carbide material with a k value of less than about four.
What is needed, therefore, is a method of depositing a plasma enhanced chemical vapor deposition silicon carbide based thin film that is substantially oxygen free and which has a dielectric constant of less than about four.